In recent years, as various types of data have been computerized and used on computers, storage devices such as disk array devices have become more important that are capable of efficiently storing therein large amounts of data independently from computers. In the disk array device, by introducing a redundant arrays of inexpensive disks (RAID) technology, reliability is enhanced compared with a simple disk device. In addition, in general, by embedding a cache memory, an access time for data is shortened.
In the RAID technology, using, for example, a method (RAID-1) for memorizing same data in a plurality of disks, a method (RAID-5) for dispersing and memorizing parity information in a disk, or the like, reliability is enhanced. In addition to this, it has been known that reliability is enhanced using a method for performing data protection by writing, into a disk, information called a block check code, a method (mirroring) for saving same data using two cache memories, or the like.
In addition to the above-mentioned logical data protection, artifices have been developed that are used for enhancing physical or electric reliability. As one of such artifices, a technique has also been known that avoids loss of data in processing during a power failure. The summary of a technique applied to a disk array device during a power failure is as follows. When the disk array device has detected the power failure, a controller module (CM) halts running processing, and protects data (cache data) within a volatile cache memory, which is to disappear owing to power shutoff. Here, as a data protection operation, there are two methods such as a memory backup method and a cache destage method.
The memory backup method is a method for causing a cache memory to make a transition to a low-power mode such as self-refresh at the time of a power failure and continuing supplying electric power from a battery to the cache memory in a state where power consumption is suppressed. In the memory backup method, since it is desirable to continue supplying electric power to the cache memory, a time period during which it is possible to back up and hold data in the cache memory is several days. Accordingly, in a case where an external power source is shut off for a long time period, there is a possibility that the backup data is lost. However, since it is possible to back up data to the cache memory with, for example, a low voltage of about 1.8 V and discharging of a small current, it is possible to downsize the battery.
The cache destage method is a method for supplying electric power from a battery at the time of a power failure and writing data within a cache memory into a non-volatile memory. To write data within a cache memory into a non-volatile memory is called destage. In the cache destage method, since cache data is written into the non-volatile memory, no restriction is put on a time period during which it is possible to back up and hold the cache data. In this regard, however, a time taken for backup processing in which the cache data is written into the non-volatile memory is dependent on the capacity of the cache memory or the number of non-volatile memories serving as writing destinations and ranges from several tens of seconds to several tens of minutes in some cases. In addition, in the cache destage method, the number of circuits to which electric power is to be supplied at this time of backup processing is larger than the memory backup method. Therefore, for example, a high voltage of about 12 V and discharging of a large current are desired in writing the cache data into the non-volatile memory, and a capacity desired for the battery becomes large.
Here, with reference to FIG. 15 to FIG. 18, power systems of storage devices to which the above-mentioned memory backup method and cache destage method are applied will be specifically described. In addition, FIG. 15 and FIG. 16 are diagrams illustrating power systems at the time of a normal operation and at the time of a power failure, respectively, in a storage device to which the memory backup method is applied. In addition, FIG. 17 and FIG. 18 are diagrams illustrating power systems at the time of a normal operation and at the time of a power failure, respectively, in a storage device to which the cache destage method is applied.
Controller enclosures (CEs) illustrated in FIG. 15 to FIG. 18 are provided between host computers (hereinafter, referred to as “hosts”) not illustrated and disk enclosures (DEs) not illustrated and perform management of resources in storage devices and so forth. In the CE, two respective CMs indicated as a CM#0 and a CM#1, two respective power supply units (PSUs) indicated as a PSU#0 and a PSU#1, and three respective battery backup units (BBUs) indicated as a BBU#0 to a BBU#2 are provided.
At the time of the normal operation, the PSUs generate system power using external power sources supplied from the outside of a device, and charge the individual BBUs at the same time as supplying the system power to the individual CMs to cause the device to operate. The BBU#0 to BBU#2 supply electric power to the individual CMs at the time of the occurrence of a power failure. In addition, the BBU#0 to BBU#2 include respective battery control units (BCUs) indicated as a BCU#0 to a BCU#2 and respective battery units (BTUs) indicated as a BTU#0 to a BTU#2, respectively. Each BCU controls charging and discharging of each BTU.
In addition, each CM includes a central processing unit (CPU), a cache memory (Cache), a non-volatile memory, a fan, a host interface (Host I/F), and a disk interface (Disk I/F). The CPU executes processing in accordance with an operating system (OS) or the like, performs various kinds of control, and fulfills various kinds of functions by executing a program saved in the non-volatile memory. The non-volatile memory saves therein various kinds of information in addition to the above-mentioned program. The cache memory is an area primarily storing therein data whose usage frequency is high, as cache data. The fan cools the CPU. The host I/F performs interface control between the host and the CPU, and performs data communication between the host and the CPU. The disk I/F performs interface control between the disk of the DE and the CPU, and performs data communication between the disk of the DE and the CPU.
In the power system at the time of the normal operation of the storage device to which the memory backup method is applied, the two PSUs generate system power using the external power sources, and charge the individual BBUs at the same time as supplying the system power to the individual CMs to cause the device to operate, as illustrated by solid line arrows in FIG. 15. At this time, in each CM, the electric power is supplied to all of the CPU, the non-volatile memory, the cache memory, the fan, the host I/F, and the disk I/F. On the other hand, when a power failure has occurred, the external power sources have been shut off, and no system power has been supplied from the two PSUs, power feeding for the cache memory serving as a backup target within each CM is performed by discharging from the three BBUs, as illustrated by solid line arrows in FIG. 16. Owing to this, backup processing for protecting data held in the cache memory is performed.
In the power system at the time of the normal operation of the storage device to which the cache destage method is applied, the two PSUs charge the individual BBUs at the same time as supplying the system power to the individual CMs to cause the device to operate, in the same way as the memory backup method, as illustrated by solid line arrows in FIG. 17. At this time, in each CM, electric power is supplied to all of the CPU, the non-volatile memory, the cache memory, the fan, the host I/F, and the disk I/F. On the other hand, when a power failure has occurred, the external power sources have been shut off, and no system power has been supplied from the two PSUs, power feeding for the CPU, the non-volatile memory, the cache memory, and the fan serving as backup targets within each CM is performed by discharging from the three BBUs, as illustrated by solid line arrows in FIG. 18. In addition, during the power feeding, cache destage processing for writing data within the cache memory into the non-volatile memory is executed.
In this way, in the case of the memory backup method, while the BBUs perform backup of power supply on the cache memories when backup is performed owing to a power failure or the like, the CPU, the non-volatile memory, the fan, the host I/F, and the disk I/F are out of the backup. On the other hand, in the case of the cache destage method, backup targets based on the BBUs at the time of backup are the CPU, the non-volatile memory, the cache memory, and the fan, and the host I/F and the disk I/F are backup non-targets. As techniques of the related art, Japanese Laid-open Patent Publication No. 2005-10972, Japanese Laid-open Patent Publication No. 2005-346321, Japanese Laid-open Patent Publication No. 2007-264755, and Japanese Laid-open Patent Publication No. 2009-5451 have been known.